Programmable integrated circuit (IC) devices are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of programmable IC, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Other types of programmable ICs include complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), and programmable array logic (PAL) devices. For all of these programmable ICs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other programmable ICs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These programmable ICs are known as mask programmable devices. Programmable ICs can also be implemented in other ways, e.g., using fuse or antifuse technology. The phrase “programmable IC” can include, but is not limited to, these devices and further can encompass devices that are only partially programmable. For example, one type of programmable IC includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
In some situations, it is desirable to be able to stop the clock of a circuit design, or a portion of a circuit design, implemented within a programmable IC. For example, during design and/or testing, a designer may wish to stop the clock of a circuit design and view the values of particular circuit components or signals. In other cases, it is desirable to allow the circuit design to continue operating albeit in a step-wise fashion in which the circuit design is permitted to advance cycle-by-cycle, where the operation of the circuit design is paused for evaluation after each clock cycle.
One technique for achieving such detailed control over the clock of a circuit design is through a technique called clock gating. One type of clock gating circuit involves a dedicated clock buffer that selectively passes a clock signal according to an enable signal applied to the clock buffer. Another type of clock gating circuit utilizes a clock multiplexer that selectively passes the clock signal or a static, unchanging signal, which is the equivalent of passing no clock signal. Depending upon the particular type of clock gating circuit used, the clock buffer, or the clock multiplexer, is coupled to a clock control module. The clock control module implements application specific logic to generate gating signals based upon pre-defined conditions detected within the circuit design being monitored in the programmable IC. The gating signals generated within the clock control module drive the enable signal of the clock buffer or the select signal of the clock multiplexer. De-asserting the enable signal of a clock buffer or selecting a signal with a steady voltage to pass through a clock multiplexer can freeze the clock supplied to downstream circuit designs in the programmable IC. For ease of illustration, the phrase “clock buffer” is used herein to refer to a clock buffer, a clock multiplexer, or any other circuit that may be used within a clock gating circuit to stop or stall a clock signal.
To ensure the proper operation of clock gating, the clock control module must meet setup and hold timing requirements of the clock buffer. When the clock control module is complex or purely combinational, meeting timing requirements may be difficult, if not infeasible, particularly at higher clock rates. In such cases, the clock control module may significantly limit the maximum achievable frequency of the clock, and thus, any circuit designs of the programmable IC utilizing that clock.
One way of ensuring that the timing requirements of the clock buffer are met is to pipeline the clock gating circuit. Pipelining can reduce the critical path delay to the clock buffer. While critical path delays are reduced, latency is incorporated into the clock gating signal, thereby delaying the arrival of the clock gating signal to the clock buffer. Therefore, the clock of the circuit design is not stopped at the exact cycle at which a decision is made to stop the clock. The clock gating signal requires time to propagate through each stage of pipelining to reach the clock buffer before the clock is actually stopped. This latency, while addressing the timing requirements of the clock buffer, is problematic when one wishes to observe the state of a circuit design at the particular clock cycle in which the condition for stopping the clock is detected. By the time the clock control signal reaches the clock buffer, the desired state of the circuit design no longer exists, as the clock has advanced by one or more clock cycles beyond the desired stopping point.